> DATE: Fri Sep 09 21:18 CDT 2022

Update on my engineering hobbies

I've decided that my first engineering hobbyist project will be a simple microprocessor design. I want to write my own instruction set architecture (not RISC-V, as I had suggested in the previous post) and create a simple single-stage CPU. Depending on how complicated I make things for myself, I might upgrade it to a pipelined architecture. To help simplify things, my arithmetic logic unit (ALU) would only support integer operations. I've got some architecting to do before I write any SystemVerilog¹ for my design, but I'm looking forward to the design process. Stay tuned for some hand-drawn schematics.

Coincidentally, I received some training this week on SystemVerilog at work. There are some significant additional features that it has over Verilog (which I used in college). Especially when it comes to testing and providing random stimulus. I won't be attending the training on UVM² (the unified verification model), but I should be able to do some outside research to become minimally competent.

In preparation for the HDL³ work, I attempted to install Xilinx Vivado — twice. On both occasions the installer would internally hung near the completion of the install. I'm not sure if I need to install the USB cable drivers first or if there is a missing dynamic library. By the way, why are USB cable drivers an issue for a piece of enterprise software in an industry where most if not all design software runs on Linux? That point aside, I think the issue is more likely to do with a missing dynamically-linked library (librdi_commontasks.so) that the Vivado executable complains about when I run it directly. Pop!_OS is not exactly on the list of supported OSes for this tool, so maybe next time I'll try installing it on Fedora since it is much more like RHEL. I forget the exact relationship between RHEL and Fedora, but one is upstream of the other. It's probably Fedora so that the features have a larger test surface before they get sent to enterprise customers.

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SystemVerilog (Wikipedia)

Universal Verification Methodology (Wikipedia)

Hardware description language (Wikipedia)